The present invention relates to integrated circuits and more particularly to integrated circuit memory devices having an automatic refreshing function.
Integrated circuits have been widely used in various fields, and there are many types of integrated circuits.
In order to check functions of integrated circuits, it has been practiced that relationships between inputs - outputs are observed. This technique is effective for integrated circuits having combination logic circuits such as AND, NOR gates since an input to the integrated circuit and its relevant output therefrom can be obtained through a small lapse of time or almost at the same time. However, for integrated circuits having sequential logic circuits such as shift registers, and memory circuits, an output is obtained after a predetermined time has elapsed from the application of an input. Therefore, it has been difficult to check the function of such integrated circuits by observing input-output characteristics. This problem is very typical in an integrated circuit memory (IC memory) having an automatic or internal refreshing function in which a refresh operation for memory cells is internally performed repeatedly without receiving any refresh address information and refresh timing signals. The above type IC memory has a refresh timer circuit and an auto-refresh timing signal generator. When a refresh control signal applied to the refresh timer circuit from the outside is kept at an active level. the refresh timer circuit produces an internal refresh command signal intermittently and the auto-refresh timing signal generator produces a refresh timing signal for allowing an internal refresh operation in response to the internal command signal. In this memory, as long as the refresh control signal is kept active, refresh of memory cells is sequentially conducted without necessity of control from the outside. Heretofore, a long period of time has been required to evaluate a data-holding function of memory cells in such memory because a holding time of memory cells is generally 10 seconds or more and generally two to three times the holding time is employed in evaluation for the sake of safety. In this point of view, if it is possible to observe the internal signal for controlling the refresh operation directly, evaluation of memories would be conducted effectively. However, the number of pins of such memories has been limited to a certain number, e.g. 16, according to the commercial specification or standard, and therefore there has been no allowance to provide an additional pin for observing the internal signal.